Ok, looking at v507

SCL+ = 1.12uS (too short)
SCL- = 2.40uS (ok, but possibly still "too short" for 100K resistor)

SDA RiseTime to +5 = 31.2uS ~= 32KHz

This is too long a rise time with the Fan installed for even 100KHz operation. (hi/lo times == 5uS/5uS)

I'm stuck to test without my scope since I can't do measurements without it on the line. So I would say if anyone has problems with the I2C devices on the bus, to change out the 100K to 5.1K.

I think it works by the luck of the draw as most of the bus ops are WRITEs where Mark has control of how long he wants to delay between writing a 0 or 1. (With 1's being a longer "wait" time before asserting SCL)

If someone tried readbacks, they'd have to wait a while before each clock (32uS). Even with those delayed writes of 1's, the risetime only allows for about 3.3V level. SO it works - but only because it's coded to.

What would you guys like to do from here?

-Ben